Embedded Controls by Design, LLC
Electronic Design and Consulting Services
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Embedded Controls by Design, LLC Electronic Design and Consulting Services |
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These are some of the board that I designed while working on Virtuoso system
at Vari-Lite, Inc.
The Virtuoso Console was recognized with a 2001 Emmy
Award for Engineering Excellence.
Console Main CPU. 
This board has a 68040 and two main communication ports. The first is a Ethernet port capable of 10/100 operation and 100BaseFX. The second is a IEEE1394 port. Custom hardware allows data to be transferred between the two busses with minimal processor overhead.
Network Interface Motherboard 
The NIF provides the interface between the Virtuoso Console and the rest of the system, The board has a 68040 processor and four 10/100 TX/FX Ethernet ports that connect to a single Ethernet MAC (LSI 80C300) via a non-blocking cross bar switch implemented in a FPGA. An expansion buss allows upto three interface boards to be added for backside communications.
Serial Interface Board.
The serial interface board provides 8 serial interface channels to interface the NIF to existing equipment. The serial interface is a manchester encoded HDLC link. Special hardware was designed so that messages could be sent and receive with little processor overhead.
NIF DMX Board 
The NIF DMX board uses its own Motorola 5307 Coldfire processor to generate two universes of DMX data. A universe of data consist of 513 bytes of asynchronous serial data. This data is transmitted by a FPGA that transmits the data without processor intervention.
DX DMX Board
The DX DMX board provide four DMX universe for the Virtuoso DX Console. The board uses a 5307 processor, an IEEE 1394 interface and an FPGA. The FPGA receives data from the TI 1394 chip and also generates the four DMX data streams.
Virtuoso Node Board.
The Node board provide six DMX universes and uses either a Ethernet interface or a serial HDLC to communicate to the console. It use the Motorola 5407 processor, the SMC LAN91C111 Ethernet MAC/Phy chip and an FPGA to provide the HDLC and serial data channels.